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SL1710
Quadrature Downconverter Preliminary Information
Supersedes October 1996 version in Media IC Handbook HB4599-1.0 DS3842 - 4.1 March 1997
The SL1710 is a quadrature downconverter, intended for use with both Professional and Consumer Digital Satellite Applications. The device contains high linearity, low noise amplifiers, quadrature mixers, plus an on-chip oscillator, operating between 350MHz and 500MHz, which may be synthesised via the differential prescaler outputs. An AGC with 18dB gain control is provided to cope with a wide range of input signal levels. I and Q outputs are via low impedance single ended amplifiers. These may be connected to a dual channel analog to digital converter such as the PCA916, VP216, VP215 or VP213, via a suitable anti-alias filter.
AGC IOUT VEEA IFINB IFIN VCCA QOUT VEEC
1
16
VCCB VCODIS VCO B VCO A VEEB PSCAL PSCALB VCCC
SL1710
MP16 FEATURES s Wide input frequency range (350-500MHz) s On chip oscillator with varactor tuning or SAW resonator operation capability s Nominal 40dB conversion gain from IF input to I and Q outputs s AGC amplifier with 18dB gain control range s I to Q phase match 90C to 2, gain match better than 1dB s Low impedance I and Q single ended outputs, with 15MHz 1dB BW s Divide by 32 prescaler outputs s Suitable for QPSK and up to 64QAM systems
Fig. 1 Pin allocation top view
ORDERING INFORMATION
SL1710/KG/MPAS SL1710/KG/MPAD (Tape and Reel)
ABSOLUTE MAXIMUM RATINGS
Storage temperature Junction temperature Supply voltage Voltage at any other pin -55C to +150C -29C to +150C -0.3 to 7.0V -0.3 to +7.0V
APPLICATIONS s Consumer digital satellite decoders s Professional digital satellite decoders s Communication systems
AGC
IFIN IFINB AGC I OUT
AGC
Q OUT
VCODIS VCOA VCOB LO
0 deg Quadrature generator
90 deg /32 PSCAL PSCALB
Fig.2. SL1710 block diagram
SL1710
ELECTRICAL CHARACTERISTICS
o o Tamb= 0 C to +80 C, Vee= 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth 15 MHz, output amplitude -11dBV These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Value Characteristic Supply voltage Supply current RF Input RF freq range Impedance VSWR Noise Figure Noise Figure variation with gain VCO VCO freq (fo) control range Phase noise Fo sensitivity to VCC Fo sensitivity to temperature Prescaler output, VOH VOL 13, 14 13, 14 13, 14 13, 14 10, 11 10, 11 10, 11 VCC-0.96 VCC-1.65 40 350 500 -85 2 40 MHz dBc/Hz External tank circuit with varicap @ 10kHz from fo. but measured in Pin 6,9,16 6,9,16 4, 5 4, 5 4, 5 4, 5 4, 5 Min 4.75 94 350 75 1.7 0.5 19 1 dB dB/dB Typ Max 5.25 110 500 Units V mA MHz ohm @ 480MHz. Fig. 4 @ 480MHz. Fig. 4 AGC at maximum gain Conditions
I or Q output. Note (1, 2) MHz/Volt Fixed external components and no KHz/C Volt Volt 60 control loop Uncompensation At 25C %Under maximum load conditions Fig. 5
Prescaler output duty cycle AGC Gain, Vagc = +2.5V Temp stability of gain Gain, Vagc = +0.5V Gain, Vagc = + VCC -0.5V AGC range I Q outputs
40 1 1 1 18 2 44 32
dB dB dB dB dB For any gain setting 0V to 5V See Fig.6 See Fig.6 480MHz local oscillator, 481 to 495MHz RF input @ -51dBV Gain set to give -11dBV, 1-15MHz baseband output into
Output impedance Output clipping level I phase lag with respect to Q IQ crosstalk Output amplitude match Baseband flatness Two tone 3rd order intercept point Im3 LO, and Sputii in IQ outputs
2, 7 2, 7 2, 7 2, 7 2, 7 2, 7 +3 1.5 88 90
8 92 20 1 1
ohm V p-p degs dB dB dB dBV
maximum load. Fig. 7 Fig. 8 1 -15MHz I releative to Q, 1 -15MHz 1-15MHz, 1k 15pF load Referred to output. @ 1MHz Output load 1kohm, 15pF, all AGC settings, 0.7V pk-pk output
2, 7 2, 7
28 -30
dBc dBV
1-100MHz
2
SL1710
ELECTRICAL CHARACTERISTICS (continued)
o o Tamb= 0 C to 80 C, Vee= 0V, Vcc = 4.75 to 5.25 V, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Value Characteristic Prescaler sidebands Power supply rejection Pin 2, 7 2, 7 Min 25 Typ -50 30 Max -47 Units dBV dB Conditions Measured in IQ outputs Attenuation VCC to IQ outputs, over 0-500kHz Notes: 1. The choice of L will have an effect on phase noise of the VCO 2. Target value at fo=500MHz, L (tank)=10nH, Q (tank, unloaded)=50, SSB
DESCRIPTION
The SL1710 is a quadrature downconverter, intended for high linearity, low noise digital satellite applications. It contains all the elements necessary, with the exception of the VCO tuning components, to extract baseband I and Q signals from a QPSK or QAM IF input signal. A block diagram for the SL1710 is shown in Fig. 2. In normal consumer digital satellite applications, the device is fed via a SAW filter, centred at the standard IF of 479.5MHz. A filtered single channel is therefore presented to the device, at a typical level of -51dBV. An AGC is included with 18dB of gain control, which is guaranteed to provide an overall conversion gain between 30 and 45dB from the RF input to the I and Q outputs. The quadrature mixers are fed from an on-chip oscillator which is centred on the incoming IF. The oscillator external tuning network should be fully symmetric, to ensure optimum gain and phase match. Single ended I and Q amplifiers are provided, which output a 760mV (p/p) signal, assuming a nominal -51dBV input signal and 40dB gain, suitable for driving a dual channel ADC such as the PCA 869, PCA 913 and PCA 916 via an anti-alias filter (see application notes). The ADC is normally AC coupled via two capacitors (typically 4.7F). The SL1710 also includes divide by 32 prescaler output. These may be fed to an external PLL circuit which can be used to drive the on-chip oscillator, thus forming a complete control loop. The VCO can be disabled by applying 0V to pin 15.
3
1
2
6
16
9
VCCA
VCCB
VCCC
C2 100nF /32 QOUT Q Mixer 5V VCODIS C13 3p3 LK2 1 SW1 VCO DISABLE R2 4K7 R4 110R C11 220nF SK4 Q CH O/P 2 4 3 T2 BCW31 15
VEEB VEEC
11 10 7 C21 10nF
PSCAL
Oscillator
VEEA
3
12
8
4
CN1 5V 5V 3 + C6 100pF C9 47uF LK1 1 2 5V SK3 I CH O/P C17 100pF IC2 9 P4 P3 NC Vcc 13 14 15 16 RF I/P RF I/P Vee I Mixer IOUT VCOA L1 12nH 3p9 VCOB 14 13 C12 R11 10K C16 10nF 12 2 11 D1 BB811 10 SP5611 P5 P6 P7 SCL SDA XTAL2 XTAL1 DRV CH PUMP C20 47nF 8 7 6 5 4 3 2 1 C18 18pF C19 220nF X1 4 MHz IC1 SL1710 5V C10 220nF R3 110R 4 3 T1 BCW31 C7 100nF C8 100pF DC POWER 30V SK4 5V I2C 6 5 4 3 SCL5 GND 5V0 SDA5 R8 22K R9 22K T3 BCW31 R10 4K7 30V 5V
SL1710
R5 680R
C3 100nF
C4 100pF
C5 100nF
VR1 1K
R6
4K7
R7 680R
5V
SK1 RF IN
C1 100nF
1
AGC
5 4
IFIN IFINB
R1 75R
PSCALB
L5
L6
4u7
4u7
C15 10nF
C14 10nF
Fig. 3 Demonstration board circuit diagram
SL1710
+j1 +j0.5 +j2
+j0.2
+j5
Marker Zreal Zimag
1 480MHz = 75.7 = -36.4
0
0.2
0.5
1
2
5
-j0.2
-j5
-j0.5 -j1
-j2
START 350 MHz
STOP 650 MHz
Fig.4 Typical RF input impedance
APPLICATION NOTES
These application notes should be read in conjunction with the circuit diagram Fig 3. and the PCB layout illustrated in Figs 9 and 10. An alternative oscillator configuration using a SAW Resonator is shown in the circuit diagram Fig. 11 and the PCB layout illustrated in Figs 12 and 13. These boards have been designed to permit the initial evaluation of the SL1710 performance.
SAW RESONATOR OSCILLATOR
The application detailed in Fig. 11 shows an SL1710 with a SAW Resonator controlled oscillator. In this instance the frequency accuracy and stability of the oscillator are determined by the Saw Resonator. The PCB detailed in Figs. 12 and 13 is designed to accommodate the following SAWR; Manufacturer MURATA Part No SAR479.45MB10X200
VARACTOR TUNED
The application detailed in Fig.3 uses a synthesised VCO. The tuning range of the oscillator is; Varactor line Voltage. 5 Volts 30 Volts Oscillator Frequency 458MHz 504MHz
PRESCALER OUTPUTS
The VCO frequency/32 is available at the differential prescaler outputs pins 10 and 11. This enables the on board VCO to be synthesised via a PLL.
VCO DISABLE
The on-chip oscillator can be disabled by connecting the VCO Disable (pin 15) to ground and enabled by connecting the pin to VCC via a 4K7 pull up resistor.
This configuration gives a VCO sensitivity of 1.84MHz/ Volt. The inductor L1 is a 12nF surface mount component. Different VCO centre frequencies and sensitivities can be achieved by changing the values of L1, C12 and C13. The VCO frequency is controlled by the SP5611 synthesiser which is programmed via an I2C bus. The RF input to the synthesiser is from the SL1710 prescaler outputs via RF inductors L3 and L4.
AGC
The DC voltage measured at TP1 should be adjusted using VR1 to read 2.5 volts with respect to VEE. this voltage equates to the nominal centre of the AGC control curve. The control voltage applied to pin 1 can be varied between 0.5 Volts (maximum gain) and VCC -0.5 Volts minimum gain)
5
SL1710
I & Q OUTPUTS
The I and Q output stages of the SL1710 are sensitive to the loads connected to them. To avoid degrading the output signals resistive loads connected to these pins should always be 1K or greater with a parallel capacitance of 15pF or less For evaluation purposes this makes the output unsuitable for connection to test equipment via normal coaxial cables. To alleviate this problem the application board is fitted with emitter follower buffer amplifiers which allow the connection of loads as low as 50 via coaxial cables without loading the output stages of the SL1710. These buffer amplifiers can be either connected in circuit, or bypassed by changing the position of Links 1 and 2.
This technique may be used in a real application where the SL1710 is used to drive and ADC via an anti-alias filter. Great care must be taken to ensure that the loading conditions stated above are not exceeded when designing the anti-alias filter section. Use of an emitter follower buffer is the easiest way to alleviate this constraint. With the AGC voltage adjusted to 2.5 Volts apply an input signal to the IF IN (pin 5) and monitor the Base Band output level at the I and Q outputs. Adjust the RF input level until an output level of 760mV pk-pk is achieved. For best performance this level should not exceeded.
Vcc 2 2K PRESCALER OUTPUT 15pF
Fig.5 Maximum prescaler output load
6
SL1710
50.00 45.00
GAIN (dB)
40.00 33.00 30.00 25.00 0 1 2 3 4 5
Vagc (V)
Fig. 6 AGC operation
IQ OUTPUT 15pF 1K
Fig. 7 Maximum IQ output load
Marker 1 2 3
Freq 500KHz 15MHz 30MHz
Zreal 3.5 4.5 56
Zimag 0.5 32 92
+j0.2 +j0.5 2
+j1 +j2
+j5 3
0 1
0.2
0.5
1
2
5
-j0.2
-j5
-j0.5
-j2 -j1
START.010MHz
STOP 30.MHz
Fig. 8 Output impedance
7
SL1710
Fig. 9 Demonstration PCB top view
Fig. 10 Demonstration PCB bottomview
8
CN1 5V
5V
POWER
1 C3 100pF C5 100pF C6 100nF LK1 1 3 4 VR1 1K R6 4K7 R7 680R IC1 SL1710 I CH OUT AGC VOLTS 6 VCCA VCCB C14 I Mixer C1 1 AGC 13 VCOA Osc 14 VCOB /32 QOUT Q Mixer VCODIS VEEA VEEB VEEC 8 VCO DISABLE SW1 LK2 1 2 R2 4K7 SK3 R4 110R 3 4 T2 BCW31 C13 1nF 12 3 15 7 C15 100pF 5V 1 SAW RESONATOR 2 3 4 5 IFIN 4 IFINB R1 C2 100nF 11 PSCAL 10 PSCALB IOUT SAW1 2 100nF 100pF VCCC 16 9 TP1 5V 5V 5V SK2 R3 110R C10 220nF 2 C12 1nF C7 100pF C8 100nF BCW31 C9 47uF T1 R5 680R C4 100nF +
2
3
SK1
IF IN
75R
5V
C11 220nF
Q CH OUT
SL1710
Fig. 11 SL1710 I & Q downconverter with saw resonator
9
SL1710
Fig. 12
Fig. 13
10
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